1. Field of the Invention
The invention relates to a semiconductor device comprising a memory cell array in which a bit line structure is hierarchized using global bit lines and local bit lines.
2. Description of Related Art
In recent years, miniaturization of a memory cell array has been achieved in volatile semiconductor devices such as DRAM, and thus in order to overcome a performance problem caused by an increase in the number of memory cells connected to a bit line, a configuration in which the bit lines are hierarchized into global bit lines and local bit lines has been proposed. It is required to reduce memory cell size to, for example, 6F2 or 4F2 (“F” is minimum manufacturing scale), and a bit line pitch in this case needs to be set to 2F that is a manufacturing limit. Meanwhile, in a memory cell array having a hierarchical bit line structure, respective memory cells need to be refreshed in a refresh operation such as an auto refresh mode or a self refresh mode in a predetermined period in order to retain data of the memory cells, in the same manner as the conventional configuration. Particularly, in a memory cell array employing the hierarchical bit line structure in the DRAM, it is required to suppress an increase in consumption current in the refresh operation that is caused by an increase in the number of memory cells. Also, it is required to prevent a reduction in sensing margin of sense amplifiers that is caused by a decrease in memory cell capacitance due to the miniaturization of the DRAM.
For example, Patent Reference 1 discloses a technique in which each bit line pair is divided into left and right portions at an approximate center thereof, one word line is selected for refreshing in each of the left and right portions, and a sense amplifier is arranged for each one of a set of portions of even-numbered and odd-numbered bit line pairs, and the refresh operation is performed being divided into two operations in chronological order, in order to reduce the consumption current in the refresh operation. However, when applying the technique disclosed in Patent Reference 1 to memory cells of small size such as 6F2 cell size or 4F2 cell size, it is required to employ an open bit line structure or a single-ended structure that are capable of reducing the bit line pitch.
Meanwhile, for example, Patent References 2 and 3 disclose techniques of a hierarchical sense amplifier for the purpose of preventing the reduction in sensing margin that is caused by the decrease in memory cell capacitance. In this case, a configuration in which the techniques of Patent References 2 and 3 are combined with the technique of Patent Reference 1 can be available to reduce the consumption current in the refresh operation. However, in such a configuration, there arises a problem that the sensing margin in the refresh operation is reduced by influence of coupling noise between adjacent global bit lines in the hierarchical bit line structure.
In order to deal with the above problem, for example, Patent References 4 and 5 disclose techniques in which local bit lines having an open bit line structure and global bit lines having a folded bit line structure are arranged and connected to each other and signals thereof are sensed and amplified for the purpose of cancelling common mode noise for each pair of global bit lines. Further, for example, Patent Reference 6 discloses a technique in which the local bit lines and the global bit lines are used for sensing and amplifying in the same manner as in Patent References 4 and 5, and additionally a precharge voltage is supplied to non-selected global bit lines until just before the amplifying by the sense amplifiers for the purpose of suppressing noise between adjacent bit lines in a read operation. Furthermore, Patent Reference 6 discloses a technique for cancelling the coupling noise from a pair of adjacent global bit lines by twisting the global bit lines.    [Patent Reference 1] Japanese Patent Application Laid-open No. 2006-286090 (U.S. Pat. No. 7,317,649)    [Patent Reference 2] Japanese Patent Application Laid-open No. 2008-262632 (U.S. Pat. No. 7,697,358)    [Patent Reference 3] Japanese Patent Application Laid-open No. 2008-294310 (U.S. Pat. No. 7,701,794)    [Patent Reference 4] Japanese Patent Application Laid-open No. H8-87880    [Patent Reference 5] Japanese Patent Application Laid-open No. 2000-114491 (U.S. Pat. No. 6,333,866)    [Patent Reference 6] Japanese Patent Application Laid-open No. 2007-287209 (U.S. Pat. No. 7,460,388)
According to the techniques disclosed in Patent References 4 and 5, the coupling noise from a pair of adjacent global bit lines cannot be cancelled. Further, according to the technique disclosed in Patent Reference 6, although the coupling noise can be cancelled, it is necessary to arrange two (a pair) global bit lines corresponding to one local bit line. Therefore, inevitably size of each memory cell cannot be set lower than twice the pitch of global bit lines, therefore a reduction in size of the memory cell is restricted. For example, even if the global bit lines can be arranged with a minimum pitch of 2F, the size of the memory cell needs to be 8F2 (2×2F×2F) and inevitably becomes larger than 6F2 and 4F2. Further, as disclosed in Patent Reference 6, when twisting the global bit lines, an increase in area of the memory cell array is caused by this twisting. In this manner, in the conventional memory cell array employing the hierarchical bit line structure, it is difficult to achieve the reduction in size of the memory cells, the reduction in consumption current in the refresh operation, and prevention of the reduction in sensing margin due to the coupling noise, at the same time.